The invention relates to controlling access to a memory device.
Computers, such as an embedded controller or a conventional personal computer (PC), have a central processing unit (CPU) for control purposes. This control unit, for the temporary or permanent storage of data, by which is also meant control programs or signal processes in the broadest sense, is assigned storage devices. The storage devices can be configured as an internal component of the computer or as an external device. In particular, the storage devices can be arranged on a circuit board, on which the central control unit is arranged. The connection of the central control unit to one or more storage units preferably occurs via buses, especially an address bus for transfer of addresses or address data and a data bus for transfer of application and user data.
Storage management devices are generally known, being connected between the central control unit or a cache direct access memory (CRAM), on the one hand, and a dynamic direct access memory (DRAM), on the other, in order to relieve the burden of controlling a storage access from the central control unit. There are various kinds of access to a memory, for example, a flash memory. In the case of a random access, each memory access is equally slow. In the case of a page mode access, a verification occurs within a page, regardless of the sequence of addresses. In the case of a so-called burst mode (a type of access operation by data blocks), a data region of the memory is accessed in a particular address sequence. A special problem is represented by the different waiting times or waiting conditions, depending on the type of access and the storage type being accessed, which need to be taken into account by the central control unit in connection with memory access to the particular storage.
Generally known are storage control devices that support a simple random access, as well as page and burst mode access to static memory, such as ROM, flash or SRAM, and also insert different waiting times depending on the type of access and the storage type used, such as the ARM Prime Cell Synchronous Static Memory Controller.
As a disadvantage, only the sequential accesses are executed quickly, i.e., memory access within a page or a burst. All non-sequential access requires additional waiting conditions, for example, 2-3 clock pulses as waiting time, regardless of the possible access speed to the memory. Another disadvantage is that no additional optimizations are provided to increase the proportion of the sequential accesses. Furthermore, no use of so-called “Merged IS Cycles” is provided, in which the central control unit during an internal cycle without memory access already points to the address for the next memory access, or in which the memory control device itself already places the next meaningful address in the memory. It is likewise disadvantageous that no improvement of the performance is possible when the CPU requests more narrow access to a broad storage, such as a 16-bit access to a 32-bit storage.
There is a need for a method and a device for controlling a memory access in alternative configuration, in order to control the memory access more efficiently. In particular, the number of waiting conditions required should be reduced.